Diferencia entre revisiones de «Unidad central de procesamiento»

Cada metodología se diferencia tanto en las maneras en las que están implementadas, como en la efectividad relativa que producen en el aumento del desempeño del CPU para una aplicación.<ref>It should be noted that neither [[Instruction level parallelism|ILP]] nor [[Thread level parallelism|TLP]] is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPU are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "[[embarrassingly parallel]] problems." Frequently, a computational problem that can be solved quickly with high TLP design strategies like SMP take significantly more time on high ILP devices like superescalar CPU, and vice versa.</ref>

 

''Artículo principal: [[Entubado de instrucción]] y [[superescalar]]''

[[Archivo:Fivestagespipeline.png|thumb|300px|left|Tubería básica de cinco etapas. En el mejor de los casos, esta tubería puede sostener un ratio de completado de una instrucción por ciclo.]]